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<title>PBLENDW — Blend Packed Words </title></head>
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<h1>PBLENDW — Blend Packed Words</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 3A 0E /r ib PBLENDW <em>xmm1, xmm2/m128, imm8</em></td>
<td>RMI</td>
<td>V/V</td>
<td>SSE4_1</td>
<td>Select words from <em>xmm1</em> and <em>xmm2/m128 </em>from mask specified in <em>imm8</em> and store the values into <em>xmm1</em>.</td></tr>
<tr>
<td>VEX.NDS.128.66.0F3A.WIG 0E /r ib VPBLENDW <em>xmm1, xmm2, xmm3/m128, imm8</em></td>
<td>RVMI</td>
<td>V/V</td>
<td>AVX</td>
<td>Select words from <em>xmm2</em> and <em>xmm3/m128 </em>from mask specified in <em>imm8</em> and store the values into <em>xmm1</em>.</td></tr>
<tr>
<td>VEX.NDS.256.66.0F3A.WIG 0E /r ib VPBLENDW <em>ymm1, ymm2, ymm3/m256, imm8</em></td>
<td>RVMI</td>
<td>V/V</td>
<td>AVX2</td>
<td>Select words from <em>ymm2</em> and <em>ymm3/m256 </em>from mask specified in <em>imm8</em> and store the values into <em>ymm1</em>.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RMI</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>imm8</td>
<td>NA</td></tr>
<tr>
<td>RVMI</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>imm8</td></tr></table>
<h2>Description</h2>
<p>Words from the source operand (second operand) are conditionally written to the destination operand (first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask, corresponding to a word, is “1", then the word is copied, else the word element in the destination operand is unchanged.</p>
<p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<h2>Operation</h2>
<p><strong>PBLENDW (128-bit Legacy SSE version)</strong></p>
<pre>IF (imm8[0] = 1) THEN DEST[15:0] (cid:197) SRC[15:0]
ELSE DEST[15:0] (cid:197) DEST[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] (cid:197) SRC[31:16]
ELSE DEST[31:16] (cid:197) DEST[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] (cid:197) SRC[47:32]
ELSE DEST[47:32] (cid:197) DEST[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] (cid:197) SRC[63:48]
ELSE DEST[63:48] (cid:197) DEST[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] (cid:197) SRC[79:64]
ELSE DEST[79:64] (cid:197) DEST[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] (cid:197) SRC[95:80]
ELSE DEST[95:80] (cid:197) DEST[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] (cid:197) SRC[111:96]
ELSE DEST[111:96] (cid:197) DEST[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] (cid:197) SRC[127:112]
ELSE DEST[127:112] (cid:197) DEST[127:112]</pre>
<p><strong>VPBLENDW (VEX.128 encoded version)</strong></p>
<pre>IF (imm8[0] = 1) THEN DEST[15:0] (cid:197) SRC2[15:0]
ELSE DEST[15:0] (cid:197) SRC1[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] (cid:197) SRC2[31:16]
ELSE DEST[31:16] (cid:197) SRC1[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] (cid:197) SRC2[47:32]
ELSE DEST[47:32] (cid:197) SRC1[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] (cid:197) SRC2[63:48]
ELSE DEST[63:48] (cid:197) SRC1[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] (cid:197) SRC2[79:64]
ELSE DEST[79:64] (cid:197) SRC1[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] (cid:197) SRC2[95:80]
ELSE DEST[95:80] (cid:197) SRC1[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] (cid:197) SRC2[111:96]
ELSE DEST[111:96] (cid:197) SRC1[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] (cid:197) SRC2[127:112]
ELSE DEST[127:112] (cid:197) SRC1[127:112]
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPBLENDW (VEX.256 encoded version)</strong></p>
<pre>IF (imm8[0] == 1) THEN DEST[15:0] (cid:197) SRC2[15:0]
ELSE DEST[15:0] (cid:197) SRC1[15:0]
IF (imm8[1] == 1) THEN DEST[31:16] (cid:197) SRC2[31:16]
ELSE DEST[31:16] (cid:197) SRC1[31:16]
IF (imm8[2] == 1) THEN DEST[47:32] (cid:197) SRC2[47:32]
ELSE DEST[47:32] (cid:197) SRC1[47:32]
IF (imm8[3] == 1) THEN DEST[63:48] (cid:197) SRC2[63:48]
ELSE DEST[63:48] (cid:197) SRC1[63:48]
IF (imm8[4] == 1) THEN DEST[79:64] (cid:197) SRC2[79:64]
ELSE DEST[79:64] (cid:197) SRC1[79:64]
IF (imm8[5] == 1) THEN DEST[95:80] (cid:197) SRC2[95:80]
ELSE DEST[95:80] (cid:197) SRC1[95:80]
IF (imm8[6] == 1) THEN DEST[111:96] (cid:197) SRC2[111:96]
ELSE DEST[111:96] (cid:197) SRC1[111:96]
IF (imm8[7] == 1) THEN DEST[127:112] (cid:197) SRC2[127:112]
ELSE DEST[127:112] (cid:197) SRC1[127:112]
IF (imm8[0] == 1) THEN DEST[143:128] (cid:197) SRC2[143:128]
ELSE DEST[143:128] (cid:197) SRC1[143:128]
IF (imm8[1] == 1) THEN DEST[159:144] (cid:197) SRC2[159:144]
ELSE DEST[159:144] (cid:197) SRC1[159:144]
IF (imm8[2] == 1) THEN DEST[175:160] (cid:197) SRC2[175:160]
ELSE DEST[175:160] (cid:197) SRC1[175:160]
IF (imm8[3] == 1) THEN DEST[191:176] (cid:197) SRC2[191:176]
ELSE DEST[191:176] (cid:197) SRC1[191:176]
IF (imm8[4] == 1) THEN DEST[207:192] (cid:197) SRC2[207:192]
ELSE DEST[207:192] (cid:197) SRC1[207:192]
IF (imm8[5] == 1) THEN DEST[223:208] (cid:197) SRC2[223:208]
ELSE DEST[223:208] (cid:197) SRC1[223:208]
IF (imm8[6] == 1) THEN DEST[239:224] (cid:197) SRC2[239:224]
ELSE DEST[239:224] (cid:197) SRC1[239:224]
IF (imm8[7] == 1) THEN DEST[255:240] (cid:197) SRC2[255:240]
ELSE DEST[255:240] (cid:197) SRC1[255:240]</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>(V)PBLENDW:</p>
<p> __m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask);</p>
<p>VPBLENDW:</p>
<p>__m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask)</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 4; additionally</p>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>If VEX.L = 1 and AVX2 = 0.</td></tr></table></body></html>